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? semiconductor components industries, llc, 2002 june, 2002 rev. 4 1 publication order number: mbrb3030ctl/d mbrb3030ctl switchmode ? power rectifier . . . using the schottky barrier principle with a proprietary barrier metal. these stateoftheart devices have the following features: features: ? dual diode construction may be paralleled for higher current output ? guardring for stress protection ? low forward voltage drop ? 125 c operating junction temperature ? maximum die size ? short heat sink tab manufactured not sheared! maximum ratings rating symbol value unit peak repetitive reverse voltage working peak reverse voltage dc blocking voltage v rrm v rwm v r 30 v average rectified forward current (at rated v r , t c = 115 c) per device i o 15 30 a peak repetitive forward current (at rated v r , square wave, 20 khz, t c = 115 c) i frm 30 a nonrepetitive peak surge current (surge applied at rated load conditions halfwave, single phase, 60 hz) i fsm 300 a peak repetitive reverse surge current (1.0 s, 1.0 khz) i rrm 2.0 a storage temperature range t stg 55 to +150 c operating junction temperature range t j 55 to +125 c voltage rate of change (rated v r , t j = 25 c) dv/dt 10,000 v/ s reverse energy, unclamped inductive surge (t j = 25 c, l = 3.0 mh) e as 224.5 mj device package shipping ordering information mbrb3030ctl d 2 pak d 2 pak case 418b plastic 50/rail 3 4 1 schottky barrier rectifier 30 amperes 30 volts 1 3 4 marking diagram b3030ctl = device code y = year ww = work week b3030ctl yww http://onsemi.com
mbrb3030ctl http://onsemi.com 2 thermal characteristics characteristic symbol value unit thermal resistance, junction to ambient (note 1.) r ja 50 c/w thermal resistance, junction to case r jc 1.0 c/w electrical characteristics maximum instantaneous forward voltage (note 2.) (i f = 15 a, t j = 25 c) (i f = 30 a, t j = 25 c) v f 0.44 0.51 v maximum instantaneous reverse current (note 2.) (rated v r , t j = 25 c) (rated v r , t j = 125 c) i r 2.0 195 ma 1. mounted using minimum recommended pad size on fr4 board. 2. pulse test: pulse width = 250 s, duty cycle 2.0%. all device data is aper lego except where noted. figure 1. typical forward voltage figure 2. maximum forward voltage figure 3. typical reverse current figure 4. maximum reverse current 0.7 0.1 v f , instantaneous forward voltage (volts) 10 1.0 30 0 v r , reverse voltage (volts) 1.0e+0 1.0e-1 1.0e-2 1.0e-3 1.0e-4 1.0e-5 i f , instantaneous forward current (amps) i 0.1 0.3 0.5 0.9 10 20 25 1000 t j = 125 c 75 c 25 c v f , maximum instantaneous forward voltage (volts) i f , instantaneous forward current (amps) , reverse current (amps) r v r , reverse voltage (volts) i , maximum reverse current (amps) r t j = 125 c 25 c 100 1.1 0.7 0.1 10 1.0 0.1 0.3 0.5 0.9 1000 t j = 125 c 75 c 25 c 100 1.1 15 5.0 30 0 1.0e+0 1.0e-1 1.0e-2 1.0e-3 1.0e-4 1.0e-5 10 20 25 t j = 125 c 75 c 25 c 15 5.0 75 c
mbrb3030ctl http://onsemi.com 3 figure 5. current derating figure 6. forward power dissipation 20 60 0 t c , case temperature ( c) 25 15 10 5.0 0 i o , average forward current (amps) 5.0 20 0 10 9.0 8.0 3.0 1.0 0 40 , average forward current (amps) i o 140 120 10 25 15 2.0 p fo , average power dissipation (watts) 20 freq = 20 khz dc square wave ipk/io = ipk/io = 5.0 ipk/io = 10 ipk/io = 20 dc square wave ipk/io = ipk/io = 5.0 ipk/io = 10 ipk/io = 20 100 80 6.0 4.0 5.0 7.0 t j = 125 c figure 7. typical capacitance 0.1 v r , reverse voltage (volts) 1000 0.1 0.00001 t, time (seconds) 1.0e+00 1.0e-01 1.0e-02 c, capacitance (pf) r 100 1.0 0.0001 0.001 0.01 10,000 , transient thermal resistance (normalized) t 10 100 t j = 25 c 1.0 10 r tjc(t) = r tjc*r(t) figure 8. typical unclamped inductive surge 0.00001 t, time (seconds) i 10 0.0001 100 0.001 0.01 t j = 25 c figure 9. typical thermal response , peak surge current (amps) pk
mbrb3030ctl http://onsemi.com 4 modeling reverse energy characteristics of power rectifiers prepared by: david shumate & larry walker on semiconductor products sector abstract power semiconductor rectifiers are used in a variety of applications where the reverse energy requirements often vary dramatically based on the operating conditions of the application circuit. a characterization method was devised using the unclamped inductive surge (uis) test technique. by testing at only a few different operating conditions (i.e. different inductor sizes) a safe operating range can be established for a device. a relationship between peak avalanche current and inductor discharge time was established. using this relationship and circuit parameters, the part applicability can be determined. this technique offers a power supply designer the total operating conditions for a device as opposed to the present singledatapoint approach. introduction in today's modern power supplies, converters and other switching circuitry, large voltage spikes due to parasitic inductance can propagate throughout the circuit, resulting in catastrophic device failures. concurrent with this, in an effort to provide lowloss power rectifiers, i.e., devices with lower forward voltage drops, schottky technology is being applied to devices used in this switching power circuitry. this technology lends itself to lower reverse breakdown voltages. this combination of high voltage spikes and low reverse breakdown voltage devices can lead to reverse energy destruction of power rectifiers in their applications. this phenomena, however, is not limited to just schottky technology. in order to meet the challenges of these situations, power semiconductor manufacturers attempt to characterize their devices with respect to reverse energy robustness. the typical reverse energy specification, if provided at all, is usually given as energytofailure (mj) with a particular inductor specified for the uis test circuit. sometimes the peak reverse test current is also specified. practically all reverse energy characterizations are performed using the uis test circuit shown in figure 10. typical uis voltage and current waveforms are shown in figure 11. in order to provide the designer with a more extensive characterization than the above mentioned onepoint approach, a more comprehensive method for characterizing these devices was developed. a designer can use the given information to determine the appropriateness and safe operating area (soa) of the selected device. figure 10. simplified uis test circuit high speed switch charge inductor dut gate voltage drain voltage drain current inductor charge switch free-wheeling diode v + -
mbrb3030ctl http://onsemi.com 5 suggested method of characterization figure 11. typical voltage and current uis waveforms time (s) inductor current dut reverse voltage utilizing the uis test circuit in figure 10, devices are tested to failure using inductors ranging in value from 0.01 to 159 mh. the reverse voltage and current waveforms are acquired to determine the exact energy seen by the device and the inductive current decay time. at least 4 distinct inductors and 5 to 10 devices per inductor are used to generate the characteristic current versus time relationship. this relationship when coupled with the application circuit conditions, defines the soa of the device uniquely for this application. example application the device used for this example was an mbr3035ct, which is a 30 a (15 a per side) forward current, 35 v reverse breakdown voltage rectifier. all parts were tested to destruction at 25 c. the inductors used for the characterization were 10, 3.0, 1.0 and 0.3 mh. the data recorded from the testing were peak reverse current (ip), peak reverse breakdown voltage (bvr), maximum withstand energy, inductance and inductor discharge time (see table 1). a plot of the peak reverse current versus time at device destruction, as shown in figure 12, was generated. the area under the curve is the region of lower reverse energy or lower stress on the device. this area is known as the safe operating area or soa. figure 12. peak reverse current versus time for dut time (s) 0.0005 0.001 0.0015 0.002 0.0025 0 0.003 0.0035 0.004 120 100 80 60 40 20 0 uis characterization curve safe operating area
mbrb3030ctl http://onsemi.com 6 table 1. uis test data part no. i p (a) b vr (v) energy (mj) l (mh) time ( s) 1 46.6 65.2 998.3 1 715 2 41.7 63.4 870.2 1 657 3 46.0 66.0 1038.9 1 697 4 42.7 64.8 904.2 1 659 5 44.9 64.8 997.3 1 693 6 44.1 64.1 865.0 1 687 7 26.5 63.1 1022.6 3 1261 8 26.4 62.8 1024.9 3 1262 9 24.4 62.2 872.0 3 1178 10 27.6 62.9 1091.0 3 1316 11 27.7 63.2 1102.4 3 1314 12 17.9 62.6 1428.6 10 2851 13 18.9 62.1 1547.4 10 3038 14 18.8 60.7 1521.1 10 3092 15 19.0 62.6 1566.2 10 3037 16 74.2 69.1 768.4 0.3 322 17 77.3 69.6 815.4 0.3 333 18 75.2 68.9 791.7 0.3 328 19 77.3 69.6 842.6 0.3 333 20 73.8 69.1 752.4 0.3 321 21 75.6 69.2 823.2 0.3 328 22 74.7 68.6 747.5 0.3 327 23 78.4 70.3 834.0 0.3 335 24 70.5 66.6 678.4 0.3 317 25 78.3 69.4 817.3 0.3 339 the procedure to determine if a rectifier is appropriate, from a reverse energy standpoint, to be used in the application circuit is as follows: a. obtain apeak reverse current versus timeo curve from data book. b. determine steady state operating voltage (ov) of circuit. c. determine parasitic inductance (l) of circuit section of interest. d. obtain rated breakdown voltage (bvr) of rectifier from data book. e. from the following relationships, v l d dt i(t) i (bvr ov) t l a adesignero l versus t curve is plotted alongside the device characteristic plot. f. the point where the two curves intersect is the current level where the devices will start to fail. a peak inductor current below this intersection should be chosen for safe operating. as an example, the values were chosen as l = 200 h, ov = 12 v and bvr = 35 v. figure 13 illustrates the example. note the uis characterization curve, the parasitic inductor current curve and the safe operating region as indicated. figure 13. dut peak reverse and circuit parasitic inductance current versus time time (s) 0.0005 0.001 0.0015 0.002 0.0025 0 0.003 0.0035 0.004 120 100 80 60 40 20 0 uis characterization curve safe operating area i peak time relationship due to circuit parasitics summary traditionally, power rectifier users have been supplied with singledatapoint reverseenergy characteristics by the supplier's device data sheet; however, as has been shown here and in previous work, the reverse withstand energy can vary significantly depending on the application. what was done in this work was to create a characterization scheme by which the designer can overlay or map their particular requirements onto the part capability and determine quite accurately if the chosen device is applicable. this characterization technique is very robust due to its statistical approach, and with proper guardbanding (6 ) can be used to give worstcase device performance for the entire product line. a atypicalo characteristic curve is probably the most applicable for designers allowing them to design in their own margins. references 1. borras, r., aliosi, p., shumate, d., 1993, aavalanche capability of today's power semiconductors, aproceedings, european power electronic conference ,o 1993, brighton, england 2. pshaenich, a., 1985, acharacterizing overvoltage transient suppressors,o powerconversion international, june/july
mbrb3030ctl http://onsemi.com 7 information for using the d 2 pak surface mount package minimum recommended footprints for surface mounted applications surface mount board layout is a critical portion of the total design. the footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. with the correct pad geometry, the packages will self align when subjected to a solder reflow process. mm inches 0.33 8.38 0.08 2.032 0.04 1.016 0.63 17.02 0.42 10.66 0.12 3.05 0.24 6.096 d 2 pak power dissipation the power dissipation of the d 2 pak is a function of the drain pad size. this can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. power dissipation for a surface mount device is determined by t j(max) , the maximum rated junction temperature of the die, r ja , the thermal resistance from the device junction to ambient; and the operating temperature, t a . using the values provided on the data sheet for the d 2 pak package, p d can be calculated as follows: p d = t j(max) t a r ja the values for the equation are found in the maximum ratings table on the data sheet. substituting these values into the equation for an ambient temperature t a of 25 c, one can calculate the power dissipation of the device which in this case is 2 watts. p d = 125 c 25 c = 2 watts 50 c/w the 50 c/w for the d 2 pak package assumes the recommended drain pad area of 158k mil 2 on fr4 glass epoxy printed circuit board to achieve a power dissipation of 2 watts using the footprint shown. another alternative is to use a ceramic substrate or an aluminum core board such as thermal clad ? . by using an aluminum core board material such as thermal clad, the power dissipation can be doubled using the same footprint. general soldering precautions the melting temperature of solder is higher than the rated temperature of the device. when the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. ? always preheat the device. ? the delta temperature between the preheat and soldering should be 100 c or less.* ? when preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. when using infrared heating with the reflow soldering method, the difference shall be a maximum of 10 c. ? the soldering temperature and time shall not exceed 260 c for more than 5 seconds. ? when shifting from preheating to soldering, the maximum temperature gradient shall be 5 c or less. ? after soldering has been completed, the device should be allowed to cool naturally for at least three minutes. gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. ? mechanical stress or shock should not be applied during cooling * * soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * * due to shadowing and the inability to set the wave height to incorporate other surface mount components, the d 2 pak is not recommended for wave soldering.
mbrb3030ctl http://onsemi.com 8 recommended profile for reflow soldering for any given circuit board, there will be a group of control settings that will give the desired heat pattern. the operator must set temperatures for several heating zones, and a figure for belt speed. taken together, these control settings make up a heating aprofileo for that particular circuit board. on machines controlled by a computer, the computer remembers these profiles from one operating session to the next. figure 14 shows a typical heating profile for use when soldering the d 2 pak to a printed circuit board. this profile will vary among soldering systems but it is a good starting point. factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. this profile shows temperature versus time. the line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. the two profiles are based on a high density and a low density board. the vitronics smd310 convection/infrared reflow soldering system was used to generate this profile. the type of solder used was 62/36/2 tin lead silver with a melting point between 177189 c. when this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. the components on the board are then heated by conduction. the circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. step 1 preheat zone 1 ramp" step 2 vent soak" step 3 heating zones 2 & 5 ramp" step 4 heating zones 3 & 6 soak" step 5 heating zones 4 & 7 spike" step 6 vent step 7 cooling 200 c 150 c 100 c 50 c time (3 to 7 minutes total) t max solder is liquid for 40 to 80 seconds (depending on mass of assembly) 205 to 219 c peak at solder joint desired curve for low mass assemblies desired curve for high mass assemblies 100 c 150 c 160 c 170 c 140 c figure 14. typical solder heating profile
mbrb3030ctl http://onsemi.com 9 package dimensions style 1: pin 1. base 2. collector 3. emitter 4. collector style 2: pin 1. gate 2. drain 3. source 4. drain style 3: pin 1. anode 2. cathode 3. anode 4. cathode seating plane s g d t m 0.13 (0.005) t 23 1 4 3 pl k j h v e c a dim min max min max millimeters inches a 0.340 0.380 8.64 9.65 b 0.380 0.405 9.65 10.29 c 0.160 0.190 4.06 4.83 d 0.020 0.035 0.51 0.89 e 0.045 0.055 1.14 1.40 g 0.100 bsc 2.54 bsc h 0.080 0.110 2.03 2.79 j 0.018 0.025 0.46 0.64 k 0.090 0.110 2.29 2.79 s 0.575 0.625 14.60 15.88 v 0.045 0.055 1.14 1.40 b m b style 4: pin 1. gate 2. collector 3. emitter 4. collector w w notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. 418b-01 thru 418b-03 obsolete, new standard 418b-04. f 0.310 0.350 7.87 8.89 l 0.052 0.072 1.32 1.83 m 0.280 0.320 7.11 8.13 n 0.197 ref 5.00 ref p 0.079 ref 2.00 ref r 0.039 ref 0.99 ref m l f m l f m l f variable configuration zone r n p u view ww view ww view ww 123 case 418b04 issue g d pak 2
mbrb3030ctl http://onsemi.com 10 notes
mbrb3030ctl http://onsemi.com 11 notes
mbrb3030ctl http://onsemi.com 12 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mbrb3030ctl/d switchmode is a trademark of semiconductor components industries, llc. thermal clad is a trademark of the bergquist company. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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